Advanced Interconnect and Packaging Technologies for MEMS (Micro Electro Mechanical Systems) and CMOS applications.
Abstract
A Swedish SME has developed a high density through silicon via technology for MEMS (Micro Electro Mechanical Systems) applications. The process enables a high level integration with e.g. System in Package (SIP) and a significantly reduced form factor. The company is looking for industrial partners and design houses with challenging MEMS designs and System in Package requirements. The offer includes process design support, implementation and MEMS volume manufacturing.
Description
When MEMS technology is debated in general, not rarely is the argument that the main hurdles relating to commercial implementation is packaging, interconnect and integration. The now offered process solves the inherent problems of packaging and interconnects by providing true wafer level packaging of MEMS devices.
The Swedish SME offers a range of high density through via technologies for silicon substrates that enables true "Wafer Level Packaging" MEMS designs.
Through Silicon Insulator
The company has been able to realize the idea to isolate a section of a highly doped, low resistivity silicon wafer laterally by incorporating a trench filled with an isolating material. The isolating trench most often has the shape of a square or a circle but could also take other shapes if necessary, as long as it constitutes a closed loop.
This feature significantly reduce the cross-talk between the areas - A problem often faced in mixed signal IC designs and combined systems incorporating MEMS sensors and read-out ASICs.
Through Silicon Via
The via technology also enables the integration of interconnect functions in advanced sensors, actuators and microfluidic devices, as well as unrestricted integration of other MEMS and CMOS devices on a silicon substrate.
Metal Via Process
For RF MEMS applications, the company has developed a metal-via process suitable to meet the stringent requirements of sub 50 mOhm total through wafer via resistance in combination with tough demands on hermeticity.
With a System in Package (SiP) approach, a number of integrated circuits are combined in a single module. The individual chips of a SiP are internally connected using flip-chip technology and may contain several silicon components (dies) and passive components all mounted on the same substrate, possibly also stacked on top of each other. This means that a complete functional unit can be built in a single package.
In this respect, the via technology and MEMS processing technology can be applied to realize customized silicon based Wafer Level Packaging (WLP) solutions.
This feature is particularly valuable in space constrained environments like mobile phones as it reduces the form factor and complexity of the PCB and overall design.
The Swedish company is looking for industrial partners and design houses with challenging MEMS designs and System in Package solutions. The offer includes design support in implementing the technology in the customers device and following production.
Innovative Aspects:
Key Features & Advantages:
- Reduced form factor, due to true "Wafer Level Packaging"
- Unrestricted integration of MEMS and CMOS devices on a substrate
- Zero Crosstalk in mixed signal Integrated Circuits (IC).
- A all silicon MEMS designs
